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www.irf.com ? 2008 international rectifier 1 june 7, 2010 datasheet no ? pd 97420 irs21858spbf high(dual mode) side driver features ? high side programmable ramp gate drive ? high side generic gate driver integrated using the same high side output pin ? additional high side generic gate driver ? under voltage lockout for vcc & vbs ? 5v input logic compatible ? tolerant to negative transient voltage on vs ? rohs compliant product summary topology pdp v offset 600 v i o+ & i o- (typical) 290ma & 600ma t on & t off (typical) 160ns & 160ns package options soic16n
irs21858spbf www.irf.com ? 2008 international rectifier 2 table of contents page description 3 simplified block diagram 4 typical application diagram 5 qualification information 6 absolute maximum ratings 7 recommended operating conditions 7 static electrical characteristics 8 dynamic electrical characteristics 9 timing diagram and logic truth table 10 input/output pin equivalent circuit diagram 14 lead definitions 15 lead assignments 15 package details 16 tape and reel details 17 part marking information 18 ordering information 19
irs21858spbf www.irf.com ? 2008 international rectifier 3 description the irs21858 is high voltage and programmable ramp slope control gate driver for mosfet and igbt with single high side dual mode driver and additional generic gate driver. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construc tion. the logic input is compatible with 5v standard cmos or lsttl output. the out put driver features a programm able slope control by external r and input signal. the floating channels can be used to dr ive an n-channel power mosfet or igbt in the high side configuration, which operates up to 600 volts above the com ground.
irs21858spbf www.irf.com ? 2008 international rectifier 4 simplified block diagram vcc com res1 hin2 hin1 ho vb vs vref reference generating conditioning and op- amp driving - + vse 9v regulator res2 logic & pulse generator pulse filter uvlo r r q s uvlo hin 3 ho3
irs21858spbf www.irf.com ? 2008 international rectifier 5 typical connection diagrams optional c c c ref r res2 25v max v sus panel vcc com hin3 hin1 hin2 nc nc vb ho3 ho vse res1 res2 vs irs21858 son16 nc vref r res1 linear ramp driver?s connection diagram (dual slope)
irs21858spbf www.irf.com ? 2008 international rectifier 6 qualification information ? industrial ?? qualification level comments: this family of ics has passed jedec?s industrial qualification. ir ?s consumer qualification level is granted by extensi on of the higher industrial level. moisture sensitivity level msl2 ??? 260c (per ipc/jedec j-std-020) machine model class b (per jedec standard jesd22-a115) esd human body model class 2 (per eia/jedec standard eia/jesd22-a114) ic latch-up test class i , level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sale s representative for further information. ?? ? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information.
irs21858spbf www.irf.com ? 2008 international rectifier 7 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com . symbol definition min max units v cc low side supply voltage -0.3 25 v v in logic input voltage (hin1, hin2 , hin3) com-0.3 vcc +0.3 v v vse , v vref high side inputs voltage vs-0.3 vb+0.3 v v res1 , v res2 high side inputs voltage vs-0.3 vb+0.3 v v b high side floating well supply voltage -0.3 625 v v s high side floating well supply return voltage vb-25 vb+0.3 v v ho floating gate drive output voltage vs-0.3 vb+0.3 v v ho3 floating gate drive output voltage vs-0.3 vb+0.3 v dv s /dt allowable vs offset supply trans ient relative to com - 50 v/ns p d package power dissipation @ ta<=+25oc - 1.0 w r ja thermal resistance, junction to ambient - 120 oc/w t j junction temperature -55 150 oc t s storage temperature -55 150 oc t l lead temperature (soldering, 10 seconds) - 300 oc recommended operating conditions for proper operation, the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to com . the offset rating are tested with supplies of (vcc-com) = (vb- vs)=15v. symbol definition min max units v cc low side supply voltage 10 20 v v in hin1, hin2, lin3 input voltage com v cc v v ho3 high side gate drive output voltage v s v b v v b high side floating well supply voltage v s +10 v s +20 v v res1,res2 res input voltage v s v b v v vref, vse vref and vse input voltage v s v b -3 v v s high side floating well supply offset voltage note2 600 v v ho floating gate drive output voltage v s v b v r res1 res1 resistor 50 300 k r res2 res2 resistor 2.5 300 k t a ambient temperature -40 125 oc ? v s and v b voltages will be tolerant to short negative transient spikes. these will be defined and specified in the future. ?? logic operation for vs of -5 to 600v. logic state held for vs of -5v to ?v bs . (please refer to design tip dt97-3 for more details).
irs21858spbf www.irf.com ? 2008 international rectifier 8 static electrical characteristi cs (all values are target data) (vcc-com) = (vb-vs)=15v. t a = 25oc. the v in , v in th and i in parameters are referenced to com. the v o and i o parameters are referenced to vs and are applicabl e to the respective output leads ho, ho3. the v ccuv parameters are referenced to com. the v bsuv parameters are referenced to v s . symbol definition min typ max units test conditions v ccuv + v cc supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv - v cc supply undervoltage negative going threshold 7.4 8.2 9.0 v bsuv+ v bs supply undervoltage positive going threshold 8.0 8.9 9.8 v bsuv- v bs supply undervoltage negative going threshold 7.4 8.2 9.0 v i lk high side floating well offset supply leakage current --- --- 50 a v b = v s = 600v --- 2.5 3.75 in1, 2 = 5v i qbs quiescent vbs supply current --- 1.45 2.2 ma in1, 2 = 0v i qcc quiescent vcc supply current --- 120 250 a in1,2,3 = 0v or 5v v ih logic ?1? input voltage 3.5 --- --- v il logic ?0? input voltage --- --- 0.8 v i in + logic ?1? input bias current --- 10 --- v in =5v i in - logic ?0? input bias current --- 0 --- a v in =0v io+_ ho,ho3 output high short circuit pulsed current --- 290 --- v o =15v,v in =5v, pw<=10us io-_ ho,ho3 output low short circuit pulsed current --- 600 --- ma v o =0v,v in =0v, pw<=10us v ol _ ho, ho3 low level output voltage --- 30 110 mv io=2ma v oh _ ho, ho3 high level output voltage, vbias-vo --- 50 130 mv io=2ma
irs21858spbf www.irf.com ? 2008 international rectifier 9 dynamic electrical characteristi cs (all values are target data) (vcc-com)= (vb-vs)=15v. t a = 25oc. c l = 1000pf unless otherwise specif ied. all parameters are reference to com. symbol definition min typ max units test conditions internal operational amplifier characteristics t ref_ln_ramp1 vref falling time of linear ramp reference 9v to 2v --- 277.8 --- s gbd* c ref =1nf, v se open, r res1 =100k, hin1=5v, hin2=com t ref_ln_ramp2 vref falling time of linear ramp reference 9v to 2v --- 14 --- s gbd* c ref =1nf, v se open, r res2 =4.99k, hin1=5v, hin2=5v i ref_ln_ramp1 vref dc current of linear ramp reference at 5v 22.68 25.2 27.72 ua c ref =1nf, v se open, r res1 =100k, hin1=5v, hin2=com i ref_ln_ramp2 vref dc current of linear ramp reference at 5v 450 500 550 ua c ref =1nf, v se open, r res2 =4.99k, hin1=5v, hin2=5v gm ota transconductance --- 12 --- ms cl_ho=1nf, r res1,2 open g open loop open loop gain 45 60 --- db cc =1nf, r res1,2 open bw ss small signal bandwidth --- 3.5 --- mhz cc =1nf, r res1,2 open v os input offset voltage --- 20 --- mv r res1,2 open ho sr+ output positive slew rate --- 4.5 --- v/s cl_ho=1nf, r res1,2 open cmrr common mode rejection ratio 50 65 --- db r res1,2 open psrr power supply rejection ratio 50 65 --- db r res1,2 open propagation delay characteristics t on turn-on delay (ho, ho3) --- 160 260 t off turn-off delay (ho, ho3) --- 160 260 t r turn-on rise from 10% to 90% --- 60 110 t f turn-off fall from 90% to 10% --- 20 50 mt delay matching, ho & ho3 turn- on/off 50 ns gate drive mode c l =1nf gbd*: guaranteed by design
irs21858spbf www.irf.com ? 2008 international rectifier 10 figure 1a input/output timing diag ram: linear ramp (dual slope)
irs21858spbf www.irf.com ? 2008 international rectifier 11 hin1 hin2 ho vref vse hin3 ho3 figure 1b input/output timing diagram : ho/ho3 outputs logic truth table hin1 hin2 hin3 ota of ho gate driver of ho gate driver of ho3 0 0 0 high impedance (hiz) 0 0 0 0 1 high impedance (hiz) 0 1 0 1 0 high impedance (hiz) 1 0 0 1 1 high impedance (hiz) 1 1 1 0 0 linear ramp rate controlled by res1 high impedance (hiz) 0 1 0 1 linear ramp rate controlled by res1 high impedance (hiz) 1 1 1 0 linear ramp rate controlled by res2 high impedance (hiz) 0 1 1 1 linear ramp rate controlled by res2 high impedance (hiz) 1 1 step(0/1) 1 or 0 stepwise linear (dual slope) high impedance (hiz) 1 or 0
irs21858spbf www.irf.com ? 2008 international rectifier 12 figure 2 timing definitions of v ref figure 3 switching time waveform definitions of ho and ho3
irs21858spbf www.irf.com ? 2008 international rectifier 13 figure 4 delay matching waveform definitions
irs21858spbf www.irf.com ? 2008 international rectifier 14 input/output pin equivalent circuit diagrams v b v s vse, vref esd diode esd diode r esd v b v s res1, res2 esd diode esd diode r esd
irs21858spbf www.irf.com ? 2008 international rectifier 15 lead definitions pin# symbol description 1 vcc low side supply voltage 2 com low side supply return 3 hin3 logic input for hi gh side gate driver output 4 hin1 logic input for ho ramp reference control 5 hin2 logic input for high side gate driver outputs, in phase 6 nc no connection 7 nc no connection 8 nc no connection 9 vref external programmable r/c input for ramp generation 10 vs high side gate drive floating supply return 11 res1 adjustable current source resistor input 12 res2 adjustable current source resistor input 13 vse voltage sense input 14 ho high side gate driver output 15 ho3 high side gate driver output 16 vb high side gate drive floating supply lead assignments 1 2 3 4 5 6 7 16 15 14 13 12 11 10 vcc hin2 vb ho3 vse res2 vs irs21858 so16n ho res1 hin3 hin1 com nc nc 8 9 vref nc
irs21858spbf www.irf.com ? 2008 international rectifier 16 package details: soic16n
irs21858spbf www.irf.com ? 2008 international rectifier 17 t ape and reel details: soic16n carrier tape dimension for 16soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 10.20 10.40 0.402 0.409 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial a h f e g d b c e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction
irs21858spbf www.irf.com ? 2008 international rectifier 18 part marking information
irs21858spbf www.irf.com ? 2008 international rectifier 19 ordering information standard pack base part number package type form quantity complete part number tube/bulk 45 irs21858spbf irs21858s soic16n tape and reel 2500 IRS21858STRPBF the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which ma y result from the use of this information. no license is g ranted by implication or otherwise under any patent or patent rights of inte rnational rectifier. the spec ifications mentioned in this do cument are subject to change without notice. th is document supersedes and r eplaces all information pr eviously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

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